In many electrical devices, such as switching power converters, means are required to switch a large current on and off at a fast rate. Field effect transistors FETs are often used as such power switching means, especially at high switching frequencies. One of the reasons FETs are often used in this application is that FETs generate a lower electrical energy loss when compared with other switching elements at frequencies above approximately 10 kHz.
Even though FETs generate a low electrical energy loss, it is desirable to further lower their energy loss to improve the operation efficiency of a device using a FET. Further, the electrical energy loss of a FET is converted mostly into heat, which could raise the temperature of all the circuit elements in the device. Since the performance and life of most circuit elements are adversely affected by high temperature, the reduction in heat generation by the FET will enhance the performance and reliability of not only the FET, but the device using the FET as well.
One of the major causes of electrical energy loss by a FET is the turn-off loss resulting from the FET switching from a conductive ON state to a nonconductive OFF state. This transition is not instantaneous; it takes a finite period of time. During this transistion period, the drain to source voltage of the FET increases from a value of almost zero to a high value. At the same time, the current flowing through the FET decreases from a high value to almost zero. The power loss is proportional to the product of the current and the drain to source voltage of the FET, and the energy loss is the integral of the power loss over time. During the transition period, the product of the current and the drain to source voltage of the FET could be quite large, thereby leading to a large turn-off power loss. Thus, it is desirable to turn off the FET as fast as possible so that the energy loss can be reduced.
In order to turn off a FET, the voltage of its gate terminal has to be changed. It is well known that the various layers of a semiconductor comprising a FET cause parasitic capacitors to exist between the gate, source, and drain terminals of the FET. In order to change the voltage of the gate terminal, a current is needed for discharging the parasitic capacitors associated with the gate terminal. The magnitude of the current is proportional to the rate of discharging of these capacitors. Thus, a large gate current sink is needed to turn off the FET rapidly. In order to provide such a gate current sink, a gate current sink driver capable of sinking a large current from the gate terminal is typically connected to the gate terminal of the FET.
Typically, a gate current sink driver consists of a transistor having its collector coupled to the gate terminal of a FET for sinking the necessary gate current when the transistor is turned on. In order to reduce the turn off time of a FET, it is desirable to increase the collector current of the transistor. An example of a prior art means for the fast turn off of a FET is disclosed in U.S. Pat. No. 4,903,182, issued to Pilukaitis, et al. This patent discloses the use of a supplementary drive transistor to enhance the gain of the gate current sink transistor in a FET gate current sink circuit. Additional passive circuit elements, such as bias resistors, are also needed in order to use the supplementary drive transistor taught by Pilukaitis, et al.
One of the problems with the above method is that such a supplementary drive transistor and its associated passive circuit elements take up valuable board space. Another problem is the additional cost incurred in using these circuit elements. The present invention eliminates the need for such a supplementary drive transistor.